1. Field of the Invention
The invention generally relates to memory technology. In particular, the invention relates to non-volatile magnetic memory.
2. Description of the Related Art
Computers and other digital systems use memory to store programs and data. A common form of memory is random access memory (RAM). Many memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices, are volatile memories. A volatile memory loses its data when power is removed. For example, after a conventional personal computer is powered off, the volatile memory is reloaded upon a boot up. In addition, certain volatile memories, such as DRAM devices, require periodic refresh cycles to retain their data even when power is continuously supplied.
In contrast to the potential loss of data encountered in volatile memory devices, nonvolatile memory devices retain data for long periods of time when power is removed. Examples of nonvolatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, and the like. Disadvantageously, conventional nonvolatile memories are relatively large, slow, and expensive. Further, many types of conventional semiconductor nonvolatile memories are relatively limited in write cycle capability and typically can only be programmed to store data about 10,000 times in a particular memory location. This prevents a conventional non-volatile memory device, such as a flash memory device, from being used as general purpose memory.
An alternative memory device is known as magnetoresistive random access memory (MRAM). An MRAM device uses magnetic states to retain data in its memory cells. Advantageously, MRAM devices are relatively fast, are nonvolatile, consume relatively little power, and do not suffer from a write cycle limitation. There are at least three different types of MRAM devices, including giant magneto-resistance (GMR) MRAM devices, magnetic tunnel junction (MTJ) or tunneling magneto-resistance (TMR) MRAM devices, and pseudo spin valve (PSV) MRAM devices. GMR MRAM devices separate at least two ferromagnetic layers with a metallic layer. In a MTJ MRAM device, at least two ferromagnetic layers are separated by a thin insulating tunnel barrier. A PSV MRAM device uses an asymmetric sandwich of the ferromagnetic layers and metallic layer as a memory cell, and the ferromagnetic layers are driven so that they do not switch at the same time.
An interface circuit detects and latches the memory state of a magnetic memory cell so that the contents of the cell can be provided to another circuit, such as a central processing unit (CPU). Disadvantageously, conventional circuits that latch the state of the magnetic memory cell are relatively sensitive to variations in transistor parameters, such as gate length. These sensitivities can disadvantageously increase production costs and can also cause data to be incorrectly read from the magnetic memory cell. Embodiments of the invention solve these and other problems by providing a latching circuit that is relatively less sensitive to variations in transistor parameters.